module AEC_APP(
    input clk_60m,
    input rst_n,
    input signed [15:0] mic_l,
    input signed [15:0] mic_r,
    input signed [15:0] far_l,
    input signed [15:0] far_r,
    input data_valid,
    output reg signed [15:0] AF_mic_l,
    output reg signed [15:0] AF_mic_r
);
//1.AEC模块例化
wire out_valid_o_l, out_valid_o_r;
wire signed [15:0] dout_o_l;
wire signed [15:0] dout_o_r;
AEC_Top AEC_LEFT(
    .clk(clk_60m), //input clk
    .rstn(rst_n), //input rstn
    .aec_ce(  1'b1  ), //input aec_ce
    .aec_outRequire( 1'b1 ), //input aec_outRequire
    .din_far(   far_l   ), //input [15:0] din_far
    .din_mic(   mic_l   ), //input [15:0] din_mic
    .input_valid_far(data_valid), //input input_valid_far
    .input_valid_mic(data_valid), //input input_valid_mic
    .out_valid(out_valid_o_l), //output out_valid
    .aec_ini_done(       ), //output aec_ini_done
    .input_ready_far(     ), //output input_ready_far
    .input_ready_mic(     ), //output input_ready_mic
    .dout(dout_o_l) //output [15:0] dout
);
AEC_Top AEC_RIGHT(
    .clk(clk_60m), //input clk
    .rstn(rst_n), //input rstn
    .aec_ce(  1'b1  ), //input aec_ce
    .aec_outRequire( 1'b1 ), //input aec_outRequire
    .din_far(   far_r   ), //input [15:0] din_far
    .din_mic(   mic_r   ), //input [15:0] din_mic
    .input_valid_far(data_valid), //input input_valid_far
    .input_valid_mic(data_valid), //input input_valid_mic
    .out_valid(out_valid_o_r), //output out_valid
    .aec_ini_done(       ), //output aec_ini_done
    .input_ready_far(     ), //output input_ready_far
    .input_ready_mic(     ), //output input_ready_mic
    .dout(dout_o_r) //output [15:0] dout
);
//2.输出接口
always @(posedge clk_60m or negedge rst_n) begin
    if(!rst_n) 
        AF_mic_l <= 16'd0;
    else if(out_valid_o_l) 
        AF_mic_l <= dout_o_l; 
    else 
        AF_mic_l <= AF_mic_l; 
end
always @(posedge clk_60m or negedge rst_n) begin
    if(!rst_n) 
        AF_mic_r <= 16'd0;
    else if(out_valid_o_r) 
        AF_mic_r <= dout_o_r; 
    else 
        AF_mic_r <= AF_mic_r; 
end

endmodule
